Department of Computer Science & Engineering

University of Ioannina

Computer Architecture II

Starts from:Mon, October 25, 2021

Course Feature
Class Description

Course_ID: MYE005

Weekly Hours: 5

Semester: >=6

ECTS Credits: 5

Course Homepage:http://ecourse.uoi.gr/enrol/index.php?id=1270

Description: Instruction Set Architecture (ISA): design, performance evaluation, benchmarks, types of ISAs Microprocessor programming: machine code, assembly. Implementation of a pipelined processor: dependencies, result forwarding, stalls, delayed branches. Instruction-level parallelism: superscalar processors, VLIW, out of order execution, register renaming, speculative execution, branch prediction. Memory subsystem: implementation technologies, organisation and operation of main memory, cache memory, virtual memory, address translation, TLBs, cache memories with virtual or physical address indexing/tagging. Exercises and projects on simulation and evaluation of processors and cache memories.

  • Aristides Efthymiou

    • PhD, School of Computer Science, University of Manchester, 2002
    • MSc, Department of Computer Science, University of Crete, 1995
    • BSc, Department of Computer Science, University of Crete, 1993