Publications
 

Journal articles

• A. Efthymiou, “Initialisation-based Test Pattern Generation for Asynchronous Circuits” IEEE Transactions on VLSI systems, 18(4):591-601, April 2010. DOI: 10.1109/TVLSI.2009.2013470

• A. Efthymiou, J. Bainbridge and D. Edwards, “Test Pattern Generation and Partial-Scan Methodology for an Asynchronous SoC Interconnect” IEEE Transactions on VLSI systems, 13(12):1384-1393, Dec. 2005. DOI: 10.1109/TVLSI.2005.862722

• M. Amde, T. Felicijan, A. Efthymiou, D. Edwards and L. Lavagno, “Asynchronous On-Chip Networks”, IEE Proceedings Computers and Digital Techniques, 152(2):273-283, March 2005. DOI: 10.1049/ip-cdt:20045093

• A. Efthymiou, J.D. Garside, “A CAM with mixed serial-parallel comparison for use in low energy caches”, IEEE Transactions on VLSI systems, 12(3):325-329, March 2004 (special issue on low power design, part 2). DOI: 10.1109/ASYNC.2004.1299304

• S.B. Furber, A. Efthymiou, J.D. Garside, M.J.G. Lewis, D.W. Lloyd, and S. Temple, “Power Manage- ment in the AMULET Microprocessors”, IEEE Design and Test of Computers, 18(2):42-52, Mar-Apr. 2001. DOI: 10.1109/54.914617

  1. •Y. Moisiadis, I. Bouras, A. Efthymiou, and C. Papadas, “A Fast 1-V Bootstrapped Inverter Suitable for Standard CMOS Technologies”, IEE Electronics Letters, 35(2):109-111, Jan. 1999. DOI: 10.1049/el:19990092

Book chapter

  1. • M. Amde, T. Felicijan, A. Efthymiou, D. Edwards and L. Lavagno, “Asynchronous On-Chip Networks”, System On Chip; Next Generation Electronics, Bashir Al-Hashimi (Editor), ISBN: 0-86341-552-0, IET, 2006

Conference papers

  1. • P.D. Ferguson, A. Efthymiou, T. Arslan, D. Hume, “Optimising Self‐timed FPGA circuits”, 13th Euromicro DSD Conference, Sept. 2010.

  2. •D. Koppad, A. Efthymiou, “BIST for Strongly-Indicating Asynchronous Circuits”, 17th IFIP/IEEE Conference on VLSI (VLSI-SoC), October 2009.

  3. •D. Vasudevan, A. Efthymiou, “Partial Scan Based Test Generation For Asynchronous Circuits”, 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits (DDECS 2008), April 2008. DOI: 10.1109/DDECS.2008.4538783

  4. •R. Hassan, A. Harris, N. Topham, A. Efthymiou, “Synthetic Trace-Driven Simulation of Cache Memory”, 21st Symposium on Advanced Information Networking and Applications (AINA 2007), pages 764-771, May 2007. DOI: 10.1109/AINAW.2007.345

• R. Hassan, A. Harris, N. Topham, and A. Efthymiou. “A hybrid Markov model for accurate memory reference generation”, IAENG International Conference on Computer Science. (ICCS’07) , 2007. (Best student paper award)

• A. Efthymiou, “Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive Combinational Circuits”, 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits (DDECS 2007), pages 377-382, April 2007. DOI: 10.1109/DDECS.2007.4295316

• A. Efthymiou, J.D. Garside, I.Papaefstathiou, “A Low-Power Processor Architecture Optimized for Wireless Devices”,  16th IEEE Conference on Application-specific Systems, Architectures and Processors (ASAP 2005), pages 185 - 190, July 2005. DOI: 10.1109/ASAP.2005.7

• S. Matakias, A. Arapoyanni, A. Efthymiou, Y. Tsiatouhas, T. Haniotakis, “Fast, parallel two-rail code checker with enhanced testability”, 11th IEEE International On-Line Testing Symposium (IOLTS 2005), pages 149-156, July 2005. DOI: 10.1109/IOLTS.2005.29

• A. Efthymiou, J. Bainbridge, and D. Edwards, “Adding Testability to an Asynchronous Interconnect for GALS SoCs”, 2004 IEEE Asian Test Symposium (ATS’04), pages 20-23, Nov. 2004. DOI: 10.1109/ATS.2004.20

• A. Efthymiou, W. Suntiamorntut, J. Garside and L.E.M. Brackenbury, “An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm”, 10ht Symposium on Asynchronous Circuits and Systems (ASYNC’04), pages 207-215, Apr. 2004. DOI: 10.1109/ASYNC.2004.1299304

• A. Efthymiou, C. Sotiriou, and D. Edwards, “Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits”, Design Automation and Test in Europe (DATE’04), Volume I, p. 672, Feb. 2004. DOI: 10.1109/DATE.2004.1268924

• A. Efthymiou, and J.D. Garside, “Adaptive Pipeline Structures for Speculation Control”, 9th Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC’03), pages 46-55, May 2003. DOI: 10.1109/ASYNC.2003.1199165

• A. Efthymiou, and J.D. Garside, “Adaptive Pipeline Depth Control for Processor Power-Management”, Intl. Conference on Computer Design (ICCD’02), pages 454-457, Sep. 2002. DOI: 10.1109/ICCD.2002.1106812

• A. Efthymiou and J.D. Garside, “An Adaptive Serial-Parallel CAM Architecture for Low-Power Cache Blocks”, Intl. Symposium on Low-Power Electronics and Design (ISLPED’02), pages 136-141, Aug. 2002. DOI:10.1145/566408.566445

• A. Efthymiou, J.D. Garside, and S. Temple, “A Comparative Power Analysis of an Asynchronous Processor”, 11th  Workshop on Power and Timing Modelling, Optimization and Simulation (PATMOS’01), pages 10.1.1-10, Sep. 2001

• S.B. Furber, A. Efthymiou, and M. Singh, “A Power-Efficient Duplex Communication System”, 1st Workshop on Asynchronous Interfaces: tools, techniques and implementations (AINT’2000), pages 145-150, July 2000

• M. Katevenis, P. Vatsolaki, and A. Efthymiou, “Pipelined Memory Shared Buffer for VLSI Switches”, ACM SIGCOMM’95, pages 39-48, Aug. 1995. DOI: 10.1145/217382.217406

  1. •M. Katevenis, P. Vatsolaki, A. Efthymiou, and M. Stratakis, “VC-level Flow Control and Centralized buffering in the Telegraphos Switch”, Hot Interconnects III, Aug. 1995

Theses - Technical reports

  1. •A. Efthymiou, "Asynchronous Techniques for Power-Adaptive Processing", PhD Thesis, Dept. of Computer Science, University of Manchester, UK. 

  2. •A. Efthymiou, "Design, Implementation, and Testing of a 25 Gb/s Pipelined Memory Switch Buffer in Full-Custom CMOS" Technical Report FORTH-ICS/TR-143, Institute of Computer Science, FORTH, Heraklion, Crete, Greece, Master of Science Thesis, Department of Computer Science, University of Crete. November 1995.

  3. •M. Katevenis, P. Vatsolaki, A. Efthymiou, "Pipelined Memory Organization for High Perfomance Switching and Buffering" Technical Report FORTH-ICS/TR-127, Institute of Computer Science, FORTH, Heraklio,Crete, Greece, December 1994.

Local workshop papers

  1. • A. Efthymiou, J. Bainbridge and D. Edwards, "Remedy for an asynchronous weakness: a fully-testable interconnect fabric" 4th ACiD-WG Workshop, Turku, Finland, June 2004.

  2. • A. Efthymiou and J.D. Garside, "Adaptive Pipeline Depth for Asynchronous Systems Using Collapsible Latch Controllers" 13th Asynchronous UK Forum, Cambridge, Dec. 2002.

  3. • A. Efthymiou, "Pipeline Occupancy Control for Power Adaptive Processors". 12th Asynchronous UK Forum, London, June 2002.

  4. • A. Efthymiou, "The Design of a Low-Power Asynchronous Communication System" 9th Asynchronous UK Forum, Cambridge, Dec. 2000.

  5. • A. Efthymiou, "Power Analysis of AMULET3" Future Directions in Low-Power Design Forum, Manchester, Oct. 2000.