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 Testing and Design for Testability

Delay Testing

      Path Delay Fault C-Testable ILAs
      Path Delay Fault Testing for Embedded IP Blocks

IDDQ Testing

      Extending the Viability of IDDQ Testing - A Built-In IDDQ Testing Circuit
      An Embedded IDDQ Testing Architecture and Technique
      Built-In IDDQ Sensors for IDDQ Testing

On-Line Testing

      Soft and Timing Error Detection Circuits
      An Error Detection and Correction Architecture
      Checker Circuits Design

RF Testing

      A BIST Technique for RF VCO Circuits
      A Design for Testabilty Technique for Differential LNA Circuits

Memory Testing

      A BIST Scheme and Testing Algorithm for Random Access Memories
      Test Pattern Generation for Memory NPSF Fault Testing

 Low Power Design

Logic Low Power Techniques

      A Low Power Technique for NORA Circuits
      State Assignment Algorithm for Finite State Machines

Memory Low Power Techniques

      SRAM Low Power Operation

Dynamic Voltage Scalling

      Low Cost Pipeline Architecture for DVS Based Circuits

 CMOS Circuit Design

Logic Families

      A Novel Domino Circuit Design Technique
      High Fan-In Differential Current Mirror Logic

Memory Design

      A High Density DRAM Cell with Built-In Gain Stage
      Charge Pump Circuits - Negative Voltage Level Shifters
      Memory Sense Amplifier Designs