Journals

• L. Dermentzoglou, A. Arapoyanni, and Y. Tsiatouhas, “A Bult-In-Test Circuit for RF Differential Low Noise Amplifiers,”
       IEEE Transactions on Circuits and Systems - I, vol. 57, no.7, pp. 1549-1558, 2010.

• S. Matakias, Y. Tsiatouhas, Th. Haniotakis and A. Arapoyanni, “A Current Mode, Parallel, Two-Rail Code Checker,”
       IEEE Transactions on Computers, vol. 57, no.8, pp. 1032-1045, 2008.

• Th. Haniotakis, Y. Tsiatouhas, D. Nikolos and C. Efstathiou, “Testable Designs of Multiple Precharged Domino Circuits,”
       IEEE Transactions on VLSI Systems, vol. 15, no. 4, pp. 461-465, 2007.

• Y. Tsiatouhas, “A Stress-Relaxed Negative Voltage-Level Converter,”
       IEEE Transactions on Circuits and Systems - II, vol. 54, no. 3, pp. 282-286, 2007.

• K. Limniotis, Y. Tsiatouhas, Th. Haniotakis and A. Arapoyanni, “A Design Technique for Energy Reduction in NORA CMOS Logic,”
       IEEE Transactions on Circuits and Systems - I, vol. 53, no. 12, pp. 2647-2655, 2006.

• S. Matakias, Y. Tsiatouhas, Th. Haniotakis and A. Arapoyanni, “A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs,”
       Journal of Electronic Testing: Theory and Applications, vol. 20, no. 5, pp. 517-525, 2004.

• L. Dermentzoglou, Y. Tsiatouhas, and A. Arapoyanni, “A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators,”
       Journal of Electronic Testing: Theory and Applications, vol. 20, no. 2, pp. 133-142, 2004.

• Th. Haniotakis, Y. Tsiatouhas, C. Efstathiou and D. Nikolos, “Domino-CMOS Strongly Code Disjpoint and Strongly Fault Secure 2-out-of-3 and 1-out-of-3 Code Checkers,”
       International Journal of Electronics, vol. 90, no.2, pp. 145-158, 2003.

• Y. Tsiatouhas, Y. Moisiadis, Th. Haniotakis, D. Nikolos and A. Arapoyanni, “A New Technique for I_DDQ Testing in Nanometer Technologies,”
       Integration the VLSI Journal, vol. 31, pp. 183-194, 2002.

• A. Chrisanthopoulos, Y. Moisiadis, Y. Tsiatouhas and A. Arapoyanni, “Comparative Study of Different Current Mode Sense Amplifiers in Submicron CMOS Technology,”
       IEE Proceedings on Circuits, Devices and Systems, vol. 149, no. 3, pp. 154-158, 2002.

• H.T. Vergos, Y. Tsiatouhas, Th. Haniotakis, D.Nikolos and M. Nicolaidis, “On Path Delay Fault Testing of Multiplexer-Based Shifters,”
       International Journal of Electronics, vol. 88, no. 8, pp. 923-937, 2001.

• G. Kamoulakos, Y.Tsiatouhas, A. Chrisanthopoulos and A. Arapoyianni, “A High –Density DRAM Cell with Built-In Gain Stage,”
       IEEE Transactions on Electron Devices, vol. 48, no. 6, pp. 1194-1199, 2001.

• G. Kamoulakos, Th. Haniotakis, Y. Tsiatouhas, J-P. Schoellkopf and A. Arapoyianni, “Device Simulation of an n-DMOS Cell with Trench Isolation,”
       Microelectronics Journal, vol. 32 (1), pp. 75-80, 2001.

• G. Kamoulakos, A. Chrisanthopoulos, Y. Tsiatouhas and A. Arapoyanni, “Management of Charge Pump Circuits,”
       Integration the VLSI Journal, vol. 30 (1), pp. 91-101, 2000.

Conferences and Symposia

• I. Liaperdos, L. Dermentzoglou, A. Arapoyanni and Y. Tsiatouhas, “A Test Technique and a BIST Circuit to Detect Catastrophic Faults in RF Mixers,”
       International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), April, 2011.

• Z. Zang, X. Kavousianos, K Chakrabarty and Y. Tsiatouhas, “A Robust and Reconfigurable Multi-Mode Power Gating Architecture,”
       International Conference on VLSI Design (VLSID), Jan. 2011.

• S. Valadimas, Y. Tsiatouhas, and A. Arapoyanni, “Timing Error Tolerance in Nanometer ICs,”
       16^th IEEE International On-Line Testing Symposium (IOLTS), pp. 283-288, July 2010.

• Y. Moisiadis and Y. Tsiatouhas, “A Receiver Circuit for Low-Swing Interconnect Schemes,”
       IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July, 2010.

• Th. Haniotakis, Z. Owda and Y. Tsiatouhas, “Memory-less Pipeline Dynamic Circuit Design Technique,”
       IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July, 2010.

• L. Dermentzoglou, A. Arapoyanni and Y. Tsiatouhas, “A Build-In Self-Test Technique for RF Mixers,”
       Proc. of IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, (DDECS), pp. 88-92, April 2010.

• Y. Sfikas and Y. Tsiatouhas, “Physical Design Oriented DRAM Neighborhood Pattern Sensitive Fault Testing,”
       Proc. of IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, (DDECS), pp. 108-113, April 2009. (Best Paper Award)

• A. Floros, Y. Tsiatouhas and X. Kavousianos, “The Time Dilation Scan Architecture for Timing Error Detection and Correction,”
       Proc. of IFIP/IEEE International Conference on Very Large Scale Integration, (VLSI-SoC), pp. 569-574, October 2008.

• I. Fudos, X. Kavousianos, D. Markouzis and Y. Tsiatouhas, “Placement and Routing in Computer Aided Design of Standard Cell Arrays by Exploiting the Structure of the Interconnection Graph,”
       Proc. of Computer-Aided Design Conference, (CAD), pp. 325-337, June 2008.

• Y. Tsiatouhas, A. Arapoyanni and D. Skias, “A Scan Flip-Flop for Low-Power Scan Operation,”
       Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 439-442, December 2007.

• A. Floros, Y. Tsiatouhas, A. Arapoyanni and Th. Haniotakis, “A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism,”
       Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 692-695, December 2006.

• Y. Tsiatouhas and A. Arapoyanni, “High Fan-In Differential Current Mirror Logic,”
       IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3894-3897, May 2006.

• S. Matakias, Y. Tsiatouhas, A. Arapoyanni and Th. Haniotakis, “An Embedded I_DDQ Testing Circuit and Technique,”
       12^th IEEE International Conference on Electronics, Circuits and Systems (ICECS), December 2005.

• L. Dermentzoglou, Y. Tsiatouhas, and A. Arapoyanni, “A Design for Testability Technique for Differential RF Low Noise Amplifiers,”
       Proc. of the XX Conference on Design of Circuits and Integrated Systems (DCIS), November 2005.

• S. Matakias, Y. Tsiatouhas, A. Arapoyanni, Th. Haniotakis, G. Prenat and S. Mir, “A Built-In I_DDQ Testing Circuit,”
       31^st IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 471-474, September 2005.

• S. Matakias, Y. Tsiatouhas, Th. Haniotakis, A. Arapoyanni and A. Efthimiou, “Fast, Parallel Two-Rail Code Checker with Enhanced Testability,”
       11^th IEEE International On-Line Testing Symposium (IOLTS), pp. 149-156, July 2005.

• A. Rao, Th. Haniotakis, Y. Tsiatouhas, and H. Djemil, “The Use of Pre-evaluation Phase in Dynamic CMOS Logic,”
       IEEE Computer Scociety Annual Symposium on VLSI (ISVLSI), pp. 270-271, May 2005.

• L. Dermentzoglou, Y. Tsiatouhas, and A. Arapoyanni, “A Built-In Self Test Scheme for Differential Ring Oscillators,”
       6^th IEEE International Symposium on Quality Electronic Design (ISQED), pp. 448-452, March 2005.

• A. Rao, Th. Haniotakis, Y. Tsiatouhas, and V. Kaky, “A New Dynamic Circuit Design Technique for High Performance TSC Checker Implementations,”
       10^th IEEE On-Line Testing Symposium (IOLTS), pp. 52-57, July 2004.

• S. Matakias, Y. Tsiatouhas, Th. Haniotakis and A. Arapoyanni, “Ultra Fast and Low Cost Parallel Two-Rail Code Checker Targeting High Fan-In Applications,”
       IEEE Symposium on VLSI (ISVLSI), pp. 293-296, February 2004.

• Y. Tsiatouhas, K. Limniotis, A. Arapoyanni, and Th. Haniotakis, “A Low Power NORA Circuit Design Technique Based on Charge Recycling,”
       10^th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 224-227, December 2003.

• Y. Tsiatouhas, S. Matakias, A. Arapoyanni, and Th. Haniotakis, “A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs,”
       9^th IEEE International On-Line Testing Symposium (IOLTS), pp.12-16, July 2003.

• Y. Tsiatouhas, Th. Haniotakis and A. Arapoyanni, “An Embedded I_DDQ Testing Architecture and Technique,”
       4^th IEEE International Symposium on Quality Electronic Design (ISQED), pp. 442-445, March 2003.

• A. Chrisanthopoulos, Y. Tsiatouhas, A.Arapoyanni and Th. Haniotakis, “SRAM Oriented Memory Sense Amplifier Design in 0.18um CMOS Technology,”
       IEEE International Symposium on Circuits and Systems (ISCAS), pp. V: 145-148, May 2002.

• Y. Tsiatouhas, Th. Haniotakis, D.Nikolos and A. Arapoyanni, “Extending the Viability of I_DDQ Testing in the Deep Submicron Era,”
       3^rd IEEE International Symposium on Quality Electronic Design (ISQED), pp. 100-105, March 2002. (Best Paper Award)

• A. Chrisanthopoulos, Th. Haniotakis, Y.Tsiatouhas and A. Arapoyanni, “New Test Pattern Generation Units for NPSF Oriented Memory Built-In Self Test,”
       8^th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 749-752, September 2001.

• A. Chrisanthopoulos, Y. Moisiadis, A. Varagis, Y.Tsiatouhas and A. Arapoyanni, “A New Flash Memory Sense Amplifier in 0.18um CMOS Technology,”
       8^th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 941-944, September 2001.

• Y. Tsiatouhas, A. Chrisanthopoulos, G. Kamoulakos, and Th. Haniotakis, “New Memory Sense Amplifier Designs in CMOS Technology,”
       7^th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 19-22, December 2000.

• D. Skias, Th. Haniotakis, Y. Tsiatouhas and A. Arapoyanni, “A State Assignment Algorithm for Finite State Machines,”
       7^th IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 823-826, December 2000.

• Y. Tsiatouhas, Th. Haniotakis, D. Nikolos and A. Arapoyanni, “A Versatile Built-In Self Test Scheme for Delay Fault Testing,”
       Proc. of ACM/IEEE Design Automation and Test in Europe Conference (DATE), pp. 756, March 2000.

Workshops

• L. Dermentzoglou, Y. Tsiatouhas, A. Arapoyanni and A Karagounis, “A Built-In Test Circuit for RF Single Ended Low Noise Amplifiers,”
       Proc. of IEEE North Atlantic Test Workshop (NATW), May 2008.

• S. Matakias, Y. Tsiatouhas, A. Arapoyianni, and Th. Haniotakis, “ A High Speed Circuit for Concurrent Detection of Soft Errors in CMOS ICs,”
       Workoshop on Radiation Effects on Components and Systems (RADECS), Sept. 2006.

• Y. Tsiatouhas, A. Arapoyanni, D. Nikolos and Th. Haniotakis, “A Hierarchical Architecture for Concurrent Soft Error Detection Based on Current Sensing,”
       8^th IEEE International On-Line Testing Workshop (IOLTW), pp. 56-60, July 2002.

• Y.Tsiatouhas, Th. Haniotakis, D. Nikolos and C. Efstathiou, “Concurrent Detection of Soft Errors Based on Current Monitoring,”
       7^th IEEE International On-Line Testing Workshop (IOLTW), pp. 106-110, July 2001.

• Y. Tsiatouhas, Th. Haniotakis and D.Nikolos, “A Compact Built-In Current Sensor for I_DDQ Testing,”
       Proc. of 6^th IEEE International On-Line Testing Workshop (IOLTW), pp. 95-99, July 2000.

• Y. Tsiatouhas, Y. Moisiadis, Th. Haniotakis, D.Nikolos and A. Arapoyanni, “A New Scheme for Effective I_DDQ Testing in Deep Submicron,”
       Proc. of 6^th IEEE International Workshop on Defect Based Testing (DBT), pp. 9-14, April 2000.

Last Update: April 2011