PUBLICATIONS


2013

• Y. Sfikas, Y. Tsiatouhas and Said Hamdioui, “Layout-Based Refined NPSF Model for DRAM Characterization and Testing,”
       IEEE Transactions on VLSI Systems, Accepted for publication.

• J. Liaperdos, A. Arapoyanni and Y. Tsiatouhas, “Adjustable RF Mixers’ Alternate Test Efficiency Optimization by the Reduction of Test Observables,”
       IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Accepted for publication.

• S. Valadimas, A. Floros, Y. Tsiatouhas, A. Arapoyanni and X. Kavousianos, “The Time Dilation Technique for Timing Error Tolerance,”
       IEEE Transactions on Computers, Accepted for publication.

• Z. Zang, X. Kavousianos, K. Chakrabarty and Y. Tsiatouhas, “Static Power Reduction using Variation-Tolerant and Reconfigurable Multi-Mode Power Switches,”
       IEEE Transactions on VLSI Systems, Accepted for publication.

• J. Liaperdos, A. Arapoyanni and Y. Tsiatouhas, “A Test and Calibration Strategy for Adjustable RF Circuits,”
       Springer, Analog Integrated Circuits and Signal Processing, vol. 74, no.1, pp. 175-192, 2013.

• J. Liaperdos, A. Arapoyanni and Y. Tsiatouhas, “A Bult-In Voltage Measurement Technique for the Calibration of RF Mixers,”
       IEEE Transactions on Instrumentation and Measurement, vol. 62, no.4, pp. 732-742, 2013.


2011

• I. Liaperdos, L. Dermentzoglou, A. Arapoyanni and Y. Tsiatouhas, “A Test Technique and a BIST Circuit to Detect Catastrophic Faults in RF Mixers,”
       International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), April, 2011.

• Z. Zang, X. Kavousianos, K Chakrabarty and Y. Tsiatouhas, “A Robust and Reconfigurable Multi-Mode Power Gating Architecture,”
       International Conference on VLSI Design (VLSID), Jan. 2011.


2010

• L. Dermentzoglou, A. Arapoyanni, and Y. Tsiatouhas, “A Bult-In-Test Circuit for RF Differential Low Noise Amplifiers,”
       IEEE Transactions on Circuits and Systems - I, vol. 57, no.7, pp. 1549-1558, 2010.

• S. Valadimas, Y. Tsiatouhas, and A. Arapoyanni, “Timing Error Tolerance in Nanometer ICs,”
       16th IEEE International On-Line Testing Symposium (IOLTS), pp. 283-288, July 2010.

• Y. Moisiadis and Y. Tsiatouhas, “A Receiver Circuit for Low-Swing Interconnect Schemes,”
       IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July, 2010.

• Th. Haniotakis, Z. Owda and Y. Tsiatouhas, “Memory-less Pipeline Dynamic Circuit Design Technique,”
       IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July, 2010.

• L. Dermentzoglou, A. Arapoyanni and Y. Tsiatouhas, “A Build-In Self-Test Technique for RF Mixers,”
       Proc. of IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, (DDECS), pp. 88-92, April 2010.


2009

• Y. Sfikas and Y. Tsiatouhas, “Physical Design Oriented DRAM Neighborhood Pattern Sensitive Fault Testing,”
       Proc. of IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, (DDECS), pp. 108-113, April 2009. (Best Paper Award)


2008

• S. Matakias, Y. Tsiatouhas, Th. Haniotakis and A. Arapoyanni, “A Current Mode, Parallel, Two-Rail Code Checker,”
       IEEE Transactions on Computers, vol. 57, no.8, pp. 1032-1045, 2008.

• A. Floros, Y. Tsiatouhas and X. Kavousianos, “The Time Dilation Scan Architecture for Timing Error Detection and Correction,”
       Proc. of IFIP/IEEE International Conference on Very Large Scale Integration, (VLSI-SoC), pp. 569-574, October 2008.

• I. Fudos, X. Kavousianos, D. Markouzis and Y. Tsiatouhas, “Placement and Routing in Computer Aided Design of Standard Cell Arrays by Exploiting the Structure of the Interconnection Graph,”
       Proc. of Computer-Aided Design Conference, (CAD), pp. 325-337, June 2008.
• L. Dermentzoglou, Y. Tsiatouhas, A. Arapoyanni and A Karagounis, “A Built-In Test Circuit for RF Single Ended Low Noise Amplifiers,”
       Proc. of IEEE North Atlantic Test Workshop (NATW), May 2008.


2007

• Th. Haniotakis, Y. Tsiatouhas, D. Nikolos and C. Efstathiou, “Testable Designs of Multiple Precharged Domino Circuits,”
       IEEE Transactions on VLSI Systems, vol. 15, no. 4, pp. 461-465, 2007.

• Y. Tsiatouhas, “A Stress-Relaxed Negative Voltage-Level Converter,”
       IEEE Transactions on Circuits and Systems - II, vol. 54, no. 3, pp. 282-286, 2007.

• Y. Tsiatouhas, A. Arapoyanni and D. Skias, “A Scan Flip-Flop for Low-Power Scan Operation,”
       Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 439-442, December 2007.


2006

• K. Limniotis, Y. Tsiatouhas, Th. Haniotakis and A. Arapoyanni, “A Design Technique for Energy Reduction in NORA CMOS Logic,”
       IEEE Transactions on Circuits and Systems - I, vol. 53, no. 12, pp. 2647-2655, 2006.

• A. Floros, Y. Tsiatouhas, A. Arapoyanni and Th. Haniotakis, “A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism,”
       Proc. of IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. 692-695, December 2006.

• Y. Tsiatouhas and A. Arapoyanni, “High Fan-In Differential Current Mirror Logic,”
       IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3894-3897, May 2006.
S. Matakias, Y. Tsiatouhas, A. Arapoyianni, and Th. Haniotakis, “ A High Speed Circuit for Concurrent Detection of Soft Errors in CMOS ICs,”
       Workoshop on Radiation Effects on Components and Systems (RADECS), Sept. 2006.


2005

• S. Matakias, Y. Tsiatouhas, A. Arapoyanni and Th. Haniotakis, “An Embedded IDDQ Testing Circuit and Technique,”
       12th IEEE International Conference on Electronics, Circuits and Systems (ICECS), December 2005.

• L. Dermentzoglou, Y. Tsiatouhas, and A. Arapoyanni, “A Design for Testability Technique for Differential RF Low Noise Amplifiers,”
       Proc. of the XX Conference on Design of Circuits and Integrated Systems (DCIS), November 2005.

• S. Matakias, Y. Tsiatouhas, A. Arapoyanni, Th. Haniotakis, G. Prenat and S. Mir, “A Built-In IDDQ Testing Circuit,”
       31st IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 471-474, September 2005.

• S. Matakias, Y. Tsiatouhas, Th. Haniotakis, A. Arapoyanni and A. Efthimiou, “Fast, Parallel Two-Rail Code Checker with Enhanced Testability,”
       11th IEEE International On-Line Testing Symposium (IOLTS), pp. 149-156, July 2005.

• A. Rao, Th. Haniotakis, Y. Tsiatouhas, and H. Djemil, “The Use of Pre-evaluation Phase in Dynamic CMOS Logic,”
       IEEE Computer Scociety Annual Symposium on VLSI (ISVLSI), pp. 270-271, May 2005.

• L. Dermentzoglou, Y. Tsiatouhas, and A. Arapoyanni, “A Built-In Self Test Scheme for Differential Ring Oscillators,”
       6th IEEE International Symposium on Quality Electronic Design (ISQED), pp. 448-452, March 2005.


2004

• S. Matakias, Y. Tsiatouhas, Th. Haniotakis and A. Arapoyanni, “A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs,”
       Journal of Electronic Testing: Theory and Applications, vol. 20, no. 5, pp. 517-525, 2004.

• L. Dermentzoglou, Y. Tsiatouhas, and A. Arapoyanni, “A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators,”
       Journal of Electronic Testing: Theory and Applications, vol. 20, no. 2, pp. 133-142, 2004.

• Th. Haniotakis, Y. Tsiatouhas, C. Efstathiou and D. Nikolos, “Domino-CMOS Strongly Code Disjpoint and Strongly Fault Secure 2-out-of-3 and 1-out-of-3 Code Checkers,”
       International Journal of Electronics, vol. 90, no.2, pp. 145-158, 2003.

• Y. Tsiatouhas, Y. Moisiadis, Th. Haniotakis, D. Nikolos and A. Arapoyanni, “A New Technique for IDDQ Testing in Nanometer Technologies,”
       Integration the VLSI Journal, vol. 31, pp. 183-194, 2002.

• A. Chrisanthopoulos, Y. Moisiadis, Y. Tsiatouhas and A. Arapoyanni, “Comparative Study of Different Current Mode Sense Amplifiers in Submicron CMOS Technology,”
       IEE Proceedings on Circuits, Devices and Systems, vol. 149, no. 3, pp. 154-158, 2002.

• H.T. Vergos, Y. Tsiatouhas, Th. Haniotakis, D.Nikolos and M. Nicolaidis, “On Path Delay Fault Testing of Multiplexer-Based Shifters,”
       International Journal of Electronics, vol. 88, no. 8, pp. 923-937, 2001.

• G. Kamoulakos, Y.Tsiatouhas, A. Chrisanthopoulos and A. Arapoyianni, “A High –Density DRAM Cell with Built-In Gain Stage,”
       IEEE Transactions on Electron Devices, vol. 48, no. 6, pp. 1194-1199, 2001.

• G. Kamoulakos, Th. Haniotakis, Y. Tsiatouhas, J-P. Schoellkopf and A. Arapoyianni, “Device Simulation of an n-DMOS Cell with Trench Isolation,”
       Microelectronics Journal, vol. 32 (1), pp. 75-80, 2001.

• G. Kamoulakos, A. Chrisanthopoulos, Y. Tsiatouhas and A. Arapoyanni, “Management of Charge Pump Circuits,”
       Integration the VLSI Journal, vol. 30 (1), pp. 91-101, 2000.



Last Update: May 2013